The present invention relates to a semiconductor packaging technology, and more particularly to a multi-chip package (MCP) with a spacer.
It has long been desired to provide low-cost semiconductor chip packages that are lighter, smaller, with higher speed, multi-function, and improved reliability. In order to satisfy this goal, a multi-chip packaging technique has been developed. The multi-chip package comprises identical or various types of plural chips being assembled into one single unit package. Compared to using plural packages, where each package comprises only a single chip, the multi-chip package has the advantages of miniaturization, low weight and high mounting density.
These multi-chip packages are classified into two types, i.e., a vertical-stacking type and a parallel-aligning type. The former reduces mounting area, while the latter simplifies the manufacturing process and reduces package thickness. In order to achieve miniaturization and low weight, the vertical-stacking type has been more commonly used in multi-chip packages. One conventional vertical-stacking type of the multi-chip package is described below.
FIG. 1 is a cross-sectional view of a conventional multi-chip package 510. The multi-chip package 510 comprises a first chip 511 mounted on a substrate 520 and a second chip 513 mounted on the first chip 511. The active surfaces of the first and second chips 511 and 513, respectively, face upward. The back surfaces of the first and second chips 511 and 513, respectively, are mounted on the substrate 520, and the first chip 511, respectively. Chip pads 512 of the first chip 511 are electrically connected to bonding pads 521 by bonding wires 535 and chip pads 514 of the second chip 513 are electrically connected to bonding pads 523 by bonding wires 537. The first chip 511, the second chip 513, and the other electrical connection elements on the substrate 520 are encapsulated with an encapsulant such as an epoxy molding resin, thereby forming a package body 541. Solder balls 543 are attached to the bottom surface of the substrate 520 and serve as external connection terminals.
The conventional multi-chip package comprises plural semiconductor chips, thereby achieving higher electrical performance and higher integration at a low-cost. Further, the area-arrayed external connection terminals of the multi-chip package satisfy the trend of ever-increasing numbers of input/output pins.
However, in the conventional multi-chip package structure, there are limits to the type and size of the chips. That is, it is difficult to stack the upper chip in an edge pad type on the lower chip in a center pad type. Also, it is difficult to stack plural center pad type chips.
Further, since the chip requires a bonding area on its surface for wire-bonding, as chips are stacked upward, the size of the upper chip should be reduced to provide the necessary bonding area. If the upper chip is bigger in size than the lower chip, the chip pads of the lower chip may be covered by the upper chip, thereby preventing wire-bonding between the chip pads of the lower chip and the bonding pads of the substrate.
Moreover, with the conventional multi-chip package structure, it is difficult to effectively control the length of the wire loop of the bonding wires.